LTTS cuts design cycle time by 40% thanks to Cadence

L&T Technology Services (LTTS) reduced its design cycle time for mobile camera and memory devices by three weeks, or nearly 40 percent, by adopting the Cadence Clarity 3D Solver to analyze interconnects, including both 10G and 25G Ethernet and MIPI signals.
Cadence at a trade event
The Clarity 3D Solver enabled LTTS to achieve gold-standard accuracy with faster extraction, which allowed them to explore what-if scenarios and create more robust designs.

When analyzing MIPI camera sensor signals with their legacy solution, LTTS was unable to extract accurate interconnect models of the wire bond structures. By importing from the Cadence Allegro Implementation Platform, the Clarity 3D Solver could easily perform accurate gold-standard extraction of signals including wire bonds and nearby power and ground structures.

Cadence Sigrity SystemSI technology was then used to verify signal integrity interface compliance. LTTS eliminated delays and conversions as it could generate S-parameter models quickly. As a result, they achieved a better design faster, without the manual effort previously required.

Because LTTS was able to conduct multiple iterations in a day, they could perform more what-if analysis for design optimization. Realizing the Clarity 3D Solver’s many advantages, LTTS was able to shorten design cycle time from eight weeks to five—a nearly 40 percent reduction.

Previously simulations required a separate server, but the Clarity 3D Solver’s efficient use of memory and distributed computing allowed LTTS to run them on a laptop. This gives LTTS confidence that acquiring additional on-premises or cloud compute resources could reduce the design cycle, said Ben Gu, vice president of multi-physics system analysis in the Custom IC & PCB Group at Cadence.

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