Samsung doubles wafer productivity of V-NAND Flash device

Samsung Electronics has announced the mass production of its first 3-bit multi-level-cell (MLC) three-dimensional (3D) Vertical NAND (V-NAND) flash memory, for use in solid state drives (SSDs).

The 3-bit V-NAND is Samsung’s latest second generation V-NAND device, which utilizes 32 vertically stacked cell layers per NAND memory chip. Each chip provides 128 gigabits (Gb) of memory storage.

According to Samsung, the use of 3 bit-per-cell, 32-layer vertically stacked cell arrays sharply raises the efficiency of memory production. Compared to Samsung’s 10 nanometer-class 3-bit planar NAND flash, the new 3-bit V-NAND has more than doubled wafer productivity.

In Samsung’s V-NAND chip structure, each cell is electrically connected to a non-conductive layer using charge trap flash (CTF) technology. Each cell array is vertically stacked on top of one another to form multibillion-cell chips.

“With the addition of a whole new line of high density SSDs that is both performance- and value-driven, we believe the 3-bit V-NAND will accelerate the transition of data storage devices from hard disk drives to SSDs,” said Jaesoo Han, senior vice president, Memory Sales & Marketing, Samsung Electronics.

“The wider variety of SSDs will increase our product competitiveness as we further expand our rapidly growing SSD business,” Han added.

The new V-NAND improves on Samsung’s first generation V-NAND (24 layer cells) launched in August 2013. The second generation V-NAND (32-layer) cell array structure was launched in May 2014.

The industry’s first 3-bit 3D V-NAND will considerably expand market adoption of V-NAND memory, to SSDs suitable for general PC users, in addition to efficiently addressing the high-endurance storage needs of most servers today, Samsung said.

[email protected]

Related News

Latest News

Latest News