Intel announced that the Intel Agilex 7 with the R-Tile chiplet is shipping production-qualified devices in volume.
This is the first FPGA with PCIe 5.0 and CXL capabilities and the only FPGA with hard intellectual property (IP) supporting these interfaces, Intel’s Programmable Solutions Group said.
“Customers are leveraging R-Tile, with PCIe Gen 5 and CXL, to accelerate software and data analytics, cutting the processing time from hours to minutes,” Shannon Poulin, Intel corporate vice president and general manager of the Programmable Solutions Group, said.
Using Agilex 7 with R-Tile, customers can seamlessly connect their FPGAs with processors, such as 4th Gen Intel Xeon Scalable processors, with the highest bandwidth processor interfaces to accelerate targeted data center and high performance computing (HPC) workloads.
Agilex 7’s architecture enables customers to deploy customized technology – at scale with hardware speeds based on their specific needs – to reduce overall design costs and development processes and to expedite execution to achieve optimal data center performance.
Agilex 7 FPGAs with the R-Tile chiplet deliver leading technology capabilities with 2-times faster PCIe 5.0 bandwidth as well as 4-times higher CXL bandwidth per port when compared to other competitive FPGA products.
Adding FPGAs with CXL memory to Xeon-based servers while using transparent page placement’s (TPP) efficient page placement improves Linux performance by up to 18 percent, according to a white paper from Meta and the University of Michigan.
UnifabriX demonstrated its CXL-enabled Smart Memory Node on multiple performance benchmarks, with one showing a 28 percent increase in the HPCG (high-performance conjugate gradient) benchmark score while utilizing 2-times more 4th Gen Xeon cores for HPC workloads.
