Today, AMD introduced the latest addition to its lineup of cost-optimized FPGAs and adaptive SoCs, the AMD Spartan UltraScale+ FPGA family. This announcement marks a significant advancement in performance and efficiency for a broad spectrum of I/O-intensive applications at the edge.
The Spartan UltraScale+ devices boast the industry’s highest I/O to logic cell ratio among FPGAs built on 28nm and lower process technology. With a focus on delivering cost and power-efficient performance, these devices offer up to 30 percent lower total power consumption compared to the previous generation. Moreover, they come equipped with an extensive set of security features, making them the most robust in the AMD Cost-Optimized Portfolio.
Kirk Saban, Corporate Vice President of Adaptive and Embedded Computing Group at AMD, emphasized the legacy of the Spartan FPGA family, which has contributed to numerous groundbreaking achievements over the past 25 years. He highlighted the enhanced security features, common design tools, and long product lifecycles of the Spartan UltraScale+ family, underscoring AMD’s commitment to delivering cost-optimized products tailored to customer needs.
Designed for edge computing, Spartan UltraScale+ FPGAs offer flexible I/O interfacing and power-efficient compute capabilities. They enable seamless integration and efficient interfacing with multiple devices or systems to address the proliferation of sensors and connected devices. With the industry’s highest I/O to logic cell ratio and support for voltage up to 3.3V, these FPGAs facilitate any-to-any connectivity for edge sensing and control applications.
The Spartan UltraScale+ family leverages 16nm FinFET technology and hardened connectivity to achieve up to a 30 percent reduction in power consumption compared to the 28nm Artix 7 family. It also introduces advanced features such as a hardened LPDDR5 memory controller and PCIe Gen4x8 support, ensuring both power efficiency and future-ready capabilities for customers.
In terms of security, Spartan UltraScale+ FPGAs offer cutting-edge features to protect intellectual property (IP), prevent tampering, and maximize uptime. These include support for Post-Quantum Cryptography with NIST-approved algorithms, differential power analysis protection, and enhanced single-event upset performance.
The entire AMD portfolio of FPGAs and adaptive SoCs is supported by the AMD Vivado Design Suite and Vitis Unified Software Platform, providing hardware and software designers with productivity benefits through a single designer cockpit from design to verification.
Sampling and evaluation kits for the AMD Spartan UltraScale+ FPGA family are expected to be available in the first half of 2025, with documentation already accessible and tools support scheduled to begin with the AMD Vivado Design Suite in the fourth quarter of 2024.
