Cadence Design Systems has tied up with TSMC to develop Internet of Things (IoT) intellectual property (IP) subsystem demonstration platform for TSMC’s power process.
This IP subsystem, with the support of the Cadence digital and custom/analog tools, will simplify IoT designs and accelerate the time to market for customers.
Initially targeting the TSMC 55ULP process, the Cadence IoT IP subsystem includes Cadence Tensilica Fusion digital signal processor (DSP), analog interfaces, peripheral and sensor interfaces. The subsystem will allow users the option to select an applications processor if needed for their design.
This Cadence IoT IP subsystem can be implemented in 40ULP and 28ULP as additional performance is needed for more compute intensive applications in the future. Many of the 200+ Cadence Tensilica processor licensees are already designing and producing SoCs and end products in IoT applications; such products include WiFi/IoT connectivity chips, motion plus voice sensor fusion devices, and wearables including smart watches.
Some of these next generation devices may be implemented in TSMC 55ULP over the next twelve months as the IP enablement gets more mature.
Cadence’s Fusion DSP includes options for security algorithm acceleration, wireless communications protocol processing, and power voice trigger. The Fusion DSP includes I/O interfaces that allow connection to sensor interfaces and I2C and I2S serial interface controllers.
“With our library of processor, analog, memory, and interface IP, Cadence is in a unique position to team with TSMC to create IP subsystems that give designers the ability to rapidly develop creative IoT and consumer application SoCs,” said Martin Lund, senior vice president and general manager of the IP Group at Cadence.