Samsung Electronics elaborated a comprehensive foundry process technology roadmap, accelerating its efforts to lead the semiconductor outsourcing market.
“To successfully compete in today’s fast-paced business environment, our customers need a foundry partner with a comprehensive roadmap at the advanced process nodes to achieve their business goals and objectives,” said Samsung foundry EVP, Jong Shik Yoo said at annual Foundry Forum held in Santa Clara, California.
The foundry business which was recently restructured as a separate business unit, is aimed at customers who design and manufacture faster, more power efficient chips.
Kelvin Low, a senior director of foundry marketing explained the need to create a separate business unit this way.
“As part of our commitment to play seriously in the foundry area we felt that it was best that we create an independent organization. That will result in less conflict of interest — although that’s not really an issue these days — it’s still a perception in some customers’ minds.”
Samsung started its Foundry business in 2005. Through several collaborations with Foundry customers, Samsung has become one of the major players in Foundry market.
Based on accumulated technology leadership, Samsung Foundry has developed foundry industry’s 1st 32nm HKMG process in 2010 and started first 14nm FinFET product’s mass production.
At Foundry Forum 2017, Samsung introduced following foundry process technologies and solutions:
- 8LPP (8nm Low Power Plus): 8LPP provides the most competitive scaling benefit before transitioning to EUV (Extreme Ultra Violet) lithography. Combining key process innovations from Samsung’s 10nm technology, 8LPP offers additional benefits in the areas of performance and gate density as compared to 10LPP.
- 7LPP (7nm Low Power Plus): 7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore’s law scaling, paving the way for single nanometer semiconductor technology generations.
- 6LPP (6nm Low Power Plus): 6LPP will adopt Samsung’s unique Smart Scaling solutions, which will be incorporated on top of the EUV-based 7LPP technology, allowing for greater area scaling and ultra-low power benefits.
- 5LPP (5nm Low Power Plus): 5LPP extends the physical scaling limit of FinFET structure by implementing technology innovations from the next process generation, 4LPP, for better scaling and power reduction.
- 4LPP (4nm Low Power Plus): 4LPP will be the first implementation of next generation device architecture – MBCFETTM structure (Multi Bridge Channel FET). MBCFETTM is Samsung’s unique GAAFET (Gate All Around FET) technology that uses a Nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture.
- FD-SOI (Fully Depleted – Silicon on Insulator): Well suited for IoT applications, Samsung will gradually expand its 28FDS technology into a broader platform offering by incorporating RF (Radio Frequency) and eMRAM(embedded Magnetic Random Access Memory) options. 18FDS is the next generation node on Samsung’s FD-SOI roadmap with enhanced PPA (Power/Performance/Area).
